ASIC Engineer, Power
Company: Meta Inc
Location: Denver
Posted on: May 28, 2023
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Job Description:
Summary:
Meta is hiring ASIC Power Engineers within our Infrastructure
organization to work on low level power designs. We are looking for
individuals with experience in power modeling for ASICs
(architecture to silicon), developing flows around EDA tools, and
low-power design to build efficient System on Chip (SoC) and IP for
data center applications.
Required Skills:
ASIC Engineer, Power Responsibilities:
Define the power specification at system and module level for Idle,
TDP, Typical use cases.
Develop power modeling infrastructure in Python/C++.
Work with or develop architectural simulators in order to model
performance and power.
Build power estimation flows at various levels of abstraction:
C-model, RTL, Gate, Layout.
Optimize design for low-power with the understanding of system
level concepts.
Evaluation and Implementation of low-power design techniques at
different levels of abstraction.
Power characterization on silicon: idle, TDP, use case power &
debug power issues on silicon.
Partner with vendors to drive low-power requirements for SoC
interfaces such as LPDDR, PCIe, etc. Partner with EDA tool vendors
to select and deploy the appropriate power estimation tools.
Collaborate with internal HW/SW Co-design, Architecture, Design,
DV, and Emulation teams for power flows, optimization and
estimation.
Minimum Qualifications:
Minimum Qualifications:
B.S. or M.S. degree in Computer Engineering, Computer Science or
Electrical Engineering.
Experience with modeling and design with C++/Python or an
equivalent high level language.
Experience with EDA tools and scripting languages (Python, Tcl)
used to build tools and flows for complex environments.
Bachelor's degree in Computer Science, Computer Engineering,
relevant technical field, or equivalent practical experience.
Preferred Qualifications:
Preferred Qualifications:
Experience with architectural performance and power models at SoC
and system level.
Low-power design techniques such as clock-gating, power-gating,
DVFS, AVS.
Experience architecting systems for various design scales (IP
blocks, SOC, multi-chip system) with an understanding of tradeoffs
between performance and power.
Post-silicon bringup, debug and identify issues on emulator and
RTL.
Understanding of ASIC design process and knowledge of leakage and
dynamic power, and impact of environment and manufacturing process
on power.
Experience managing multiple design releases and working with cross
functional teams to support and debug power issues.
Experience with communicating across functional internal teams and
with vendors.
Knowledge of front-end and back-end ASIC tools.
Experience with RTL design using SystemVerilog or other HDL.
Public Compensation:
$136,000/year to $195,000/year + bonus + equity + benefits
Industry: Internet
Equal Opportunity:
Meta is proud to be an Equal Employment Opportunity and Affirmative
Action employer. We do not discriminate based upon race, religion,
color, national origin, sex (including pregnancy, childbirth,
reproductive health decisions, or related medical conditions),
sexual orientation, gender identity, gender expression, age, status
as a protected veteran, status as an individual with a disability,
genetic information, political views or activity, or other
applicable legally protected characteristics. You may view our
Equal Employment Opportunity notice here. We also consider
qualified applicants with criminal histories, consistent with
applicable federal, state and local law. We may use your
information to maintain the safety and security of Meta, its
employees, and others as required or permitted by law. You may view
Meta's Pay Transparency Policy, Equal Employment Opportunity is the
Law notice, and Notice to Applicants for Employment and Employees
by clicking on their corresponding links. Additionally, Meta
participates in the E-Verify program in certain locations, as
required by law
Keywords: Meta Inc, Denver , ASIC Engineer, Power, Engineering , Denver, Colorado
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